Growth of 4H-SiC epilayers with low surface roughness and morphological defects density on 4° off-axis substrates

In situ etching and epitaxial growth have been performed on 4H-SiC 4° off-axis substrates with 100 mm diameter. In situ etching process optimizations lead to obtain step-bunching free epilayer surfaces with roughnesses of 0.2 nm and 0.8 nm, which were grown on the substrates with and without chemical mechanical polishing, respectively. Yet the epilayer surfaces free of step-bunching are more likely to suffer from various types of morphological defects than the ones with step-bunching. An increase in chlorine/silicon ratio during epitaxy can effectively suppress the appearance of defects on the step-bunching free epilayer surfaces. Using optimized epitaxial processes, we can obtain the total morphological defects density lower than 1 cm⁻² on 4H-SiC epilayers with surface roughness of 0.2 nm.

Highlights

► We presented the results on surface roughness and morphological defects of 4H-SiC epilayers on 4° off-axis substrates with 100 mm diameter.

► The impacts of the etch processes on the surface roughness of substrates and grown epilayers were shown.

► Smooth epilayer surfaces without step-bunching were obtained by optimizing etch processes.

► The increase in the Cl/Si ratio was demonstrated to effectively suppress the morphological defects on the epilayers with smooth surfaces.

► We can obtain the total morphological defects density lower than 1 cm−2 on 4H-SiC epilayers with roughness of 0.2 nm.

Source:Applied Surface Science

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Studies of 4H-SiC wafer and its epitaxial layers grown by chemical vapor deposition

We have systematically studied C- and Si-face n-4H-SiC wafers before and after the growth of epitaxial layers using an optical Nomarski microscope (ONM) and an atomic force microscope (AFM). In particular, a number of defects such as micropipes, microtubes, threading edge dislocations, and screw dislocations are identified in H2 etched C-face and Si-face SiC wafers. The properties of ohmic contact formed on the backside of the C- and Si-face wafers by metallization are investigated by ONM and AFM to observe the effect of C- and Si-face polarities. In addition to these analyses, X-ray diffraction studies are done on the metallized Si- and C-faces to determine formation of any silicides. Ni-based Schottky junctions made on the wafers and on the epitaxial layers grown on the C- and Si-face 4H-SiC are studied by means of I–V and capacitance–voltage (C–V) techniques. The difference in characteristics between the Schottky junctions on the wafer and on the epilayer is analyzed. The C–V mapping is done on several Schottky diodes, in order to find the effect of hillocks and carrot-like defects in the junctions. The Schottky junction barrier heights decreased if carrot-like defects are presented in the epilayer. The variation of capacitance with temperature for the Schottky junctions is studied by using C–V measurements and their results are discussed with effect of temperature.

Source: Physica B: Condensed Matter

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Series resistance study of Schottky diodes developed on 4H-SiC wafers using a contact of titanium or molybdenum

We have studied and compared two types of Schottky diodes prepared by the evaporation of molybdenum (Mo) and titanium (Ti) on a 4H-SiC semiconductor. The electrical characteristics of these diodes are analyzed based on the standard thermionic emission model. The main electrical parameters including the series resistance Rs, the ideality factor n and the barrier height ΦB are extracted from current–voltage–temperature (I–V–T) measurements. In the Ti/4H-SiC structure, the series resistance increases from 1.51 mΩ cm2 to 27.68 mΩ cm2 when the temperature is varied from 70 K to 450 K. In contrast, the series resistance does not exceed a 6.17 mΩ cm2 at 450 K in the Mo/4H-SiC Schottky diode. We have decomposed the series resistance into three components. The deduced static and dynamic parameters were used to define an electrical model. The switching behavior of the equivalent circuit indicates a reverse recovery time (Trr) of 1.412 ns for Ti/4H-SiC and 3.27 ns for Mo/4H-SiC.

Source: Microelectronic Engineering

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Large area optical characterization of 3 and 4 inches 4H–SiC wafers

Whole 4H–SiC 3 and 4 inches wafers optical characterization is a rapid system for assessing the quality of substrates and epitaxial layers. Spatially resolved micro-photoluminescence (μPL) and micro-Raman (μR) spectroscopy are performed on large areas allowing obtaining several structural properties as extended defect surface density, doping concentration uniformity, stress field of wafers. With our modified apparatus it is possible to perform μPL and μR fast characterization with the same resolution on the same area. Moreover it is easy to perform high resolution μPL and μR analyses on critical areas, i.e. high defective areas, for device manufacturing.

Source: Journal of Crystal Growth

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Surface photovoltage and Auger electron spectromicroscopy studies of HfO2/SiO2/4H-SiC and HfO2/Al2O3/4H-SiC structures

The electronic and chemical properties of the interface region in the structures obtained by the passivation of epitaxial n-type 4H-SiC layers with bilayers consisting of a 5 nm-thick SiO₂ or Al₂O₃ buffer film and high-κHfO₂ layer were investigated. The main aim was to estimate the influence of the passivation approach on the interface effective charge density (Q_eff) from the surface photovoltage (SPV) method and, in addition to determine the in-depth element distribution in the interface region from the Auger electron spectroscopy (AES) combined with Ar⁺ ion profiling. The structure HfO₂/SiO₂/4H-SiC exhibited slightly superior electronic properties in terms of Q_eff (in the range of −10¹¹ q cm⁻²).

Highlights

► We applied contactless surface photovoltage to assess oxide/SiC interface quality.

► 5 nm-thick SiO₂film seems to be better interlayer between SiC and HfO₂ than Al₂O₃.

► Element distribution in the oxide/SiC interface was obtained from AES profiling.

► SiO₂ buffer and transition silicate nanofilms were found from AES spectra analysis.

Source: Journal of Crystal Growth

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Crystal growth of micropipe free 4H–SiC on 4H–SiC{033(_)8} seed and high-purity semi-insulating 6H–SiC

Micropipe free c-plane 4H–SiC wafers were achieved by sublimation growth on the 4H–SiC{033(_)8} seed. 4H–SiC {033(_)8} seeds were obtained by inclining the c-plane to 〈011(_)0〉 at 54.7°. A transmission X-ray topograph of the micropipe free c-plane wafer revealed that there were no macroscopic defects with lattice displacements. Crystal growth of undoped (vanadium-free) semi-insulating 6H–SiC was carried out by our sublimation system. In order to achieve high resistivity, high-purity SiC source and controlled instruments were used for the reduction of nitrogen, boron and metal impurity backgrounds. Hence high-purity and high-resistivity 6H–SiC 2 and 3 in in diameter were developed for high-frequency power transistors.

Source: Journal of Crystal Growth

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Effect of Ar annealing temperature on SiO2/4H-SiC interface studied by spectroscopic ellipsometry and atomic force microscopy

The authors have investigated the effects of different annealing temperatures in Ar atmosphere on the SiO₂/4H-SiC interfaces by spectroscopic ellipsometry (SE) and atomic force microscopy (AFM). There is a strong correlation between the annealing temperatures and the quality of SiO₂/4H-SiC interface. Annealing at 600 °C can significantly improve the quality of SiO₂/4H-SiC interface with no transition layer. The reasons for such improvement in the quality of the SiO₂/4H-SiC interface after moderate temperature annealing at 600 °C may be explained by the formation and consumption of carbon clusters and silicon oxycarbides during annealing.

Source: Materials Science in Semiconductor Processing

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Capacitance–conductance spectroscopic investigation of interfacial oxide layer in Ni/4H–SiC (0 0 0 1) Schottky diode

In this reported work the interface properties of a process-induced thin interfacial oxide layer present between Ni and 4H–SiC substrate was examined systematically for fabricated Ni/4H–SiC (0 0 0 1) Schottky barrier diodes. Moreover, their contribution in the form of interface traps level density was investigated employing capacitance–conductance (C–C) spectroscopy techniques. The distinctive parameters of interface at Ni and 4H–SiC substrate were determined from the C–C spectroscopy under forward bias condition. The increase in capacitance value towards lower frequencies results from the presence of interface traps at the Ni/4H–SiC interface however the observed maximums peaks in the normalized conductance curve of the diode indicates the presence of an interfacial layer in the fabricated Schottky barrier diode. It has been found that the density of interface traps level decreases (1.25×10¹³–1.16×10¹³ cm⁻² eV⁻¹) and time constant of interface traps (3.16×10⁻⁵–1.47×10⁻³ s) increases with bias voltage at anode in the range of Ec-0.06 to Ec-1.06 eV from the top of conduction band toward midgap of n-type 4H–SiC substrate. Furthermore, the capture cross section was found to vary from 9.31×10⁻¹⁰ cm² in (Ec-0.06) eV to 4.43×10^–11 cm² in (Ec-1.06) eV.

Source: Physica B: Condensed Matter

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