Feb 4, 2016

Improved L-gate 4H-SiC MESFETs with partial p-type spacer

An improved L-gate 4H-SiC metal-semiconductor field-effect-transistor with partial p-type spacer (ILP-MESFET) is proposed and its electrical performance modeled. The saturation drain current of the ILP-MESFET is about 20% higher than that of a conventional (C-)MESFET and very close to that of the LP-MESFET at a gate-source voltage of −4 V. The DC bias point of the ILP-MESFET is improved compared with that of a C-MESFET. The gate-source/drain drift region partial p-type spacer can suppress the gate depletion layer extending to source/drain. The simulation resulted in a gate-source capacitance of the proposed structure that is 26% smaller than a LP-MESFET and points to improved RF performance by ILP structures.

Keywords

Growth of 4H-SiC epilayers with low surface roughness and morphological defects density on 4° off-axis substrates

In situ etching and epitaxial growth have been performed on 4H-SiC 4° off-axis substrates with 100 mm diameter. In situ etching process optimizations lead to obtain step-bunching free epilayer surfaces with roughnesses of 0.2 nm and 0.8 nm, which were grown on the substrates with and without chemical mechanical polishing, respectively. Yet the epilayer surfaces free of step-bunching are more likely to suffer from various types of morphological defects than the ones with step-bunching. An increase in chlorine/silicon ratio during epitaxy can effectively suppress the appearance of defects on the step-bunching free epilayer surfaces. Using optimized epitaxial processes, we can obtain the total morphological defects density lower than 1 cm−2 on 4H-SiC epilayers with surface roughness of 0.2 nm.

Graphical abstract

Image for unlabelled figure

Highlights

► We presented the results on surface roughness and morphological defects of 4H-SiC epilayers on 4° off-axis substrates with 100 mm diameter. ► The impacts of the etch processes on the surface roughness of substrates and grown epilayers were shown. ► Smooth epilayer surfaces without step-bunching were obtained by optimizing etch processes. ► The increase in the Cl/Si ratio was demonstrated to effectively suppress the morphological defects on the epilayers with smooth surfaces. ► We can obtain the total morphological defects density lower than 1 cm−2 on 4H-SiC epilayers with roughness of 0.2 nm.

Keywords