Chloride-based fast homoepitaxial growth of 4H-SiC films in a vertical hot-wall CVD*

Chloride-based fast homoepitaxial growth of 4H-SiC epilayers was performed on 4° off-axis 4H-SiC substrates in a home-made vertical hot-wall chemical vapor deposition (CVD) system using H2−SiH4−C2H4−HCl. The effect of the SiH4/H2 ratio and reactor pressure on the growth rate of 4H-SiC epilayers has been studied successively. The growth rate increase in proportion to the SiH4/H2 ratio and the influence mechanism of chlorine has been investigated. With the reactor pressure increasing from 40 to 100 Torr, the growth rate increased to 52 μm/hand then decreased to 47 μm/h, which is due to the joint effect of H2 and HCl etching as well as the formation of Si clusters at higher reactor pressure. The surface root mean square (RMS) roughness keeps around 1 nm with the growth rate increasing to 49 μm/h. The scanning electron microscope (SEM), Raman spectroscopy and X-ray diffraction (XRD) demonstrate that 96.7 μm thick 4H-SiC layers of good uniformity in thickness and doping with high crystal quality can be achieved. These results prove that chloride-based fast epitaxy is an advanced growth technique for 4H-SiC homoepitaxy.

Keywords: 4H-SiC epilayers;  4H-SiC substrates;  H2−SiH4−C2H4−HCl.;  SiH4/H2; 

Source: iopscience

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Stoichiometry of the ALD-Al2O3/4H–SiC interface by synchrotron-based XPS

The interface of Al2O3 with 4H-SiC is investigated with synchrotron-based high-resolution x-ray photoelectron spectroscopy to clarify the effect of post-dielectric deposition annealing processes (rapid thermal annealing (RTA) and furnace annealing (FA)) involved in device fabrication. Our results show that post-deposition annealing of Al2O3/4H-SiC up to 1100 °C forms a thin interfacial layer of SiO2 between Al2O3 and SiC, which possibly improves the dielectric properties of the system by reducing oxide charges and near-interface traps. Moreover, the formation of SiO2 at the interface gives additional band offset to the dielectric system. We have also observed that the RTA and FA processes have similar results at a high temperature of 1100 °C. Therefore, we propose that high-temperature post-oxide (Al2O3) deposition annealing of up to 1100 °C may be used in device processing, which can improve overall dielectric properties and consequently the device performance.

Keywords:  Al2O3 ;  4H-SiC;  rapid thermal annealing (RTA);  furnace annealing (FA);  SiO2;

Source:　iopscience

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Design and spectrum calculation of 4H-SiC thermal neutron detectors using FLUKA and TCAD

SiC is a promising material for neutron detection in a harsh environment due to its wide band gap, high displacement threshold energy and high thermal conductivity. To increase the detection efficiency of SiC, a converter such as ⁶LiF or ¹⁰B is introduced. In this paper, pulse-height spectra of a PIN diode with a ⁶LiF conversion layer exposed to thermal neutrons (0.026 eV) are calculated using TCAD and Monte Carlo simulations. First, the conversion efficiency of a thermal neutron with respect to the thickness of ⁶LiF was calculated by using a FLUKA code, and a maximal efficiency of approximately 5% was achieved. Next, the energy distributions of both ³H and α induced by the ⁶LiF reaction according to different ranges of emission angle are analyzed. Subsequently, transient pulses generated by the bombardment of single ³H or α-particles are calculated. Finally, pulse height spectra are obtained with a detector efficiency of 4.53%. Comparisons of the simulated result with the experimental data are also presented, and the calculated spectrum shows an acceptable similarity to the experimental data. This work would be useful for radiation-sensing applications, especially for SiC detector design.

Keywords:  4H-SiC;  Thermal neutron detector;  Simulation;  Pulse height spectra

Source: Sciencedirect

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Improved double-recessed P-buffer 4H-SiC MESFETs with partial heavy doped channel

An improved double-recessed P-buffer 4H-SiC MESFETs with partial heavy doped channel (HD-MESFET) is proposed in this paper. Compared with the double-recessed p-buffer layer (DRB-MESFET), because of the concentration gradient from the heavy doped area to the channel under the low gate, which prevents the lateral expansion of the depletion layer toward source under the gate, and increases its longitudinal width, thus the DC and frequency characteristics of the device are improved. The simulations indicate that the drain saturation current of the proposed structure increased by 18.4%. Despite a slight decrease in the breakdown voltage, the maximum output power density was still increased by 16.5%. In addition, the DC transconductance increased by 32%. Moreover, the proposed structure has an effective promotion in threshold voltage, which improves the effectiveness of the device performance.

Keywords:  4H-SiC MESFET;  Double-recessed drift regions (DRB);  Heavy doped (HD);  Drain saturation current;  DC transconductance

Source: Sciencedirect

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