Parametric investigation of the formation of epitaxial Ti3SiC2 on 4H-SiC from Al-Ti annealing

Highlights

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Growth of Ti₃SiC₂ thin films onto 4H-SiC (0 0 0 1) 8° and 4°-off substrates.

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High temperature application for SiC ohmic contact.

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Thermal annealing of Ti_-Al layers.

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Influence of the composition in the Ti_xAl_1−x alloy was investigated.

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Influence of the annealing temperature (900–1200 °C) after deposition was investigated.

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The structural investigations were mainly performed by using X-ray diffraction (XRD), and transmission electron microscopy (TEM).

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Elementary and profile characterization were performed using X-Ray photoelectron spectroscopy (XPS).

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Abstract

The growth of Ti₃SiC₂ thin films was studied onto 4H-SiC (0 0 0 1) 8° and 4°-off substrates by thermal annealing of Ti_xAl_1−x (0.5 ≤ x ≤ 1) layers. The annealing time was fixed at 10 min under Argon atmosphere. The synthesis conditions were also investigated according to the annealing temperature (900–1200 °C) after deposition. X-Ray Diffraction (XRD) and Transmission Electron Microscope (TEM) show that the layer of Ti₃SiC₂ is epitaxially grown on the 4H-SiC substrate. In addition the interface looks sharp and smooth with evidence of interfacial ordering. Moreover, during the annealing procedure, the formation of unwanted aluminum oxide was detected by using X-Ray Photoelectron Spectroscopy (XPS); this layer can be removed by using a specific annealing procedure.

Keywords

• Ti-Al alloy; 
• Ti₃SiC₂; 
• 4H-SiC; 
• XRD; 
• XPS; 
• TEM
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    Source:Sciencedirect
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A model of the off-behaviour of 4H–SiC power JFETs

Highlights

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A physical model of 4H–SiC VJFET off-behaviour up to the blocking voltage.

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Modelling of the voltage barrier as a function of V_DS and V_GS.

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Relations of the geometrical and physical parameters on I_D–V_DS characteristics.

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Good accuracy with numerical simulations and experimental measurements.

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Abstract

A physical model of the off-behaviour of Vertical Junction Field Effect Transistors (VJFETs) up to their blocking voltage limit is presented. Since the drain current, I_D, of these devices strongly depends on the amount of the voltage barrier occurring in the channel, the model is capable to describe the drain voltage dependence of the voltage barrier and of I_D from V_DS = 0 V up to maximum V_DS value (kV) sustained from device and to describe the effects of geometry and doping of channel. The accuracy of the model is proven by comparing the I_D–V_DS curves with numerical simulations of devices designed with different gate depth, channel width, and epilayer thickness. The agreement between model, numerical simulations and literature data confirms the capability of model to describe the I_D–V_DS curves of devices having a pentode or triode like behaviour.

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Graphical abstract

Keywords

• 4H Polytype of silicon carbide (4H–SiC); 
• Blocking voltage; 
• Power JFETs;
• Semiconductor device modelling
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    • Source:Sciencedirect
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    • If you need more information about SiC 4H, please visit our website:http://www.qualitymaterial.net/products.html, send us email at powerwaymaterial@gmail.com.